• OPTIMISING INDUSTRIAL IMAGING
    Lossless compression | Probative archival | Traceability

Specification for the FPGA integration of Waaves & MM Waaves

1 - Integration of the Waaves algorithm on a Stratix IV card


 
The current architecture of the SoC for Waaves implemented in a stratix IV FPGA card from ALTERA is described in figure 1. This architecure is made up of material IPs used for calculations (shown in green) :
  • Colour space conversion : Bayer to RGB to YUV
  • Wavelet transform calculation and quantification : DWT & Quantization (third-party IP)
  • Adaptive subband coding to optimize compression
Data manipulation and monitoring IPs complete these calculation IPs, shown in dark blue in figure 1:
  • the 2 image data acquisition IP, which produce the images once uncompressed : DMA write for input image and DMA read for output image
  • the 2 IP allowing access to data for calculation IPs : DMA R/W
  • the IP controling access to data in the DDR memory : DDR controller (third-party IP)
The final element in this chip is the System CPU which, to this day, is a softcore NiosII from Altera but could just as well be an FP6 processor from Cortus or other onboard processors.
 

2 - Specifications

The specifications given here describe surface requirements. These estimations indicate the resources required to integrate the Waaves and MM-Waaves algorithms on a FPGA. No technological  (technological nodes, for instance) or packaging requirements are given here.

2.1 Storage memory requirements

Our various run évaluations have allowed us to determine that dynamic emory requirements are governed by the following two functions:
  • During compression : Size = 3,8 x N - 0,05 MB
  • During decompression : Size = 3,76 x N + 0,16 MB
Note : N represents the image size in bytes, MB denotes Megabytes.

2.2 Surface requirements

The estimation provided here is for the architecture described in figure 1and is based on our current progress.
The Adaptive Subband Coding is still under development and we are only mentioning the requirements for the coding section (Henuc).

Surfaces are given in number of Altera resources used, ALUT, FlipFlop, DSP blocks and memory, internal to the FPGA.
 
2.2.1 Nios Altera

 

Table 1: Surface Resources

Legend:
  • IP1 : Bayer to RGB to YUV
  • IP2 : DWT & Quantization et DMA R/W
  • ADSW : Adaptive subband coding
  • HENUC: Hierarchical ENUmerative Coding
  • IP4 : DMA write for input image et DMA read for output image
To these resources must be added:
3,8 MB of flash memory to store the code + 64 KB of 2.2.2 Version FP6 (Cortus) cache memory 
40 K doors for the Cortus FP6 + 3,8 MB of flash memory to store the code and 64KB of cache memory.
 

Table 2 : Surface Resources

Legend:
  • IP1 : Bayer to RGB to YUV
  • IP2 : DWT & Quantization et DMA R/W
  • ADSW : Adaptive subband coding
  • HENUC : Hierarchical ENUmerative Coding
  • IP4 : DMA write for input image et DMA read for output image

3 - Frequency

These evaluations were made with a system frequency of 100 MHz.

that frequency is enough to give us an estimate of gain, compared to running on a single core processor, in other words a compression/decompression rate of 10 MB/s.

Our target frequency is 500 MHz to allow processing speeds of 50 MB/s.

4 - Input / Output

In our prototype, input-output were performed in the form of  an interconnection with a type GPIO 40 bits bus.
 
The use of a standardized parallel or series bus, for instance a AXI or SPI bus is possible, comparisons haven't been made.
 

5 - Integrating the MM-Waaves algorithm on a Stratix I card

In order to perform video compression, the MM-Waaves algorithm based on the image compression algorithm Waaves was integrated on a card based on a Altera Stratix I. 
 
The following resources represent what needs to be added for the video part.
 

5.1 MM-Waaves specifications

Table 3: Ressources required for the MM-Waaves video section MM WAAVES resources for material IP
 

5.2 Global

Table 4: Ressources required for Waaves and MM-Waaves
global waaves resources for material IP